Boundary Word Line Search and Open Block Read Methods with Reduced Read Disturb

ABSTRACT

Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for a read operation, including post-write verify reads. Non-selected word lines that are unwritten are biased with a lower read-pass voltage then is typically used. The determination of the last written word line of a block can be done in a coarse-fine search, where the word lines are divided into a number of zones to find the zone with the last written word line, which is in turn sub-divided for a finer search.

BACKGROUND

The following relates to the operation of re-programmable non-volatile memory systems such as semiconductor flash memory that record data using charge stored in charge storage elements of memory cells.

Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retains its stored data even after power is turned off. Also, unlike ROM (read only memory), flash memory is rewritable similar to a disk storage device. In spite of the higher cost, flash memory is increasingly being used in mass storage applications.

Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions. Flash memory such as Flash EEPROM allows entire blocks of memory cells to be erased at the same time.

The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.

In order to improve read and program performance, multiple charge storage elements or memory transistors in an array are read or programmed in parallel. Thus, a “page” of memory elements are read or programmed together. In existing memory architectures, a row typically contains several interleaved pages or it may constitute one page. All memory elements of a page are read or programmed together.

Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. For example, a nonvolatile memory cell may have a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.

SUMMARY

For a non-volatile memory having a plurality of blocks formed according to a NAND type architecture in which memory cells of a block are formed along multiple word lines, and in which the word lines of a block are written sequentially from a first end to a second end, a method is present to determine the last written word line in a partially written block. A coarse determination is performed, which includes dividing the word lines of the first block into a plurality of zones, each of the zones including a contiguous plurality of word lines, and determining to which of the zones the last written word line belongs, which includes a zone sensing operation on one or more of the zones. A zone sensing operation on a selected one of the zone includes: biasing word lines of the selected zone to a first read voltage; biasing the word lines of any zones between the selected zone and the first end of the first block to the first read voltage; and biasing the word lines of any zones between the selected zone and the second end of the first block to a second read voltage. The first read voltage is sufficient to allow the memory cells to conduct independently of a data state programmed thereto and the second read voltage is less than the first read voltage. With the zones of the first block so biased, the method determines whether the number of non-conducting NAND strings of the first block is below a first criterion and, in response to determining that the number of non-conducting NAND strings of the first block is below the first criterion, determining that the last written word line of the first block belongs to the selected zone. A fine determination is then performed on the determined zone to fine the last written word line.

A method is presented for the operation of a non-volatile memory system, where the non-volatile memory system includes an array of non-volatile memory cells having a plurality of blocks formed according to a NAND type architecture in which memory cells of a block are formed along multiple word lines, including a first word line, and in which the word lines of a block are written sequentially from a first end to a second end of array. A write operation on the first word line is performed and a post-write read operation of the first word line is subsequently to verify the write operation. The read operation includes determining whether the read operation includes a page of data stored on a first word line that belongs to a partially written block; and, in response to determining that the first word line belongs to a partially written block, performing a modified read operation for the first word line. A modified read operation for the first word line includes: applying a first sensing voltage along the first word line; applying a first non-selected word line read voltage along word lines between the first word line and the first end of the partially written block; and applying a second non-selected word line read voltage along one or more word lines between the first word line and the second end of the partially written block. The first non-selected word line read voltage is sufficient to allow the memory cells to conduct independent of a data state programmed in a call and the second non-selected word line read voltage is less than the first non-selected word line read voltage.

Various aspects, advantages, features and embodiments are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates schematically the main hardware components of a memory system suitable for implementing various aspects described in the following.

FIG. 2 illustrates schematically a non-volatile memory cell.

FIG. 3 illustrates the relation between the source-drain current I_(D) and the control gate voltage V_(CG) for four different charges Q1-Q4 that the floating gate may be selectively storing at any one time at fixed drain voltage.

FIG. 4 illustrates schematically a string of memory cells organized into a NAND string.

FIG. 5 illustrates an example of a NAND array 210 of memory cells, constituted from NAND strings 50 such as that shown in FIG. 4.

FIG. 6 illustrates a page of memory cells, organized in the NAND configuration, being sensed or programmed in parallel.

FIGS. 7A-7C illustrate an example of programming a population of memory cells.

FIG. 8 shows an example of a physical structure of a 3-D NAND string.

FIGS. 9-12 look at a particular monolithic three dimensional (3D) memory array of the NAND type (more specifically of the “BiCS” type).

FIG. 13 illustrates using a lowered VREAD_PARTIAL on the drain side of the selected word line when searching for the last written word line of a block.

FIG. 14 shows the use of the lower VREAD_PARTIAL to help to reduce the disturb accumulated on drain side erased word lines, thereby reducing bit error rates.

FIG. 15 graphically represents the relationship between the number of “1” bits and the number of word lines between a selected and the last written word line for different VREAD_PATIAL levels.

FIG. 16 is an example of an algorithm that intelligently decides how may word lines to skip between reads when determining a last written word line.

FIG. 17 illustrates differences in bit line settling times for different data patterns.

FIG. 18 is a block diagram to help illustrate a modified read operation using a reduced VPASS on unwritten word lines.

FIG. 19 is an exemplary flow for using a lower VREAD bias on un-programmed word lines.

FIG. 20 is a flow for a simplified embodiment for using a lower VREAD bias on un-programmed word lines.

FIG. 21 is a flowchart for an exemplary embodiment of a coarse search for the last written word line.

FIG. 22 illustrates the bias levels applied to word lines in the coarse search.

FIG. 23 is a flowchart for an exemplary embodiment of a fine search for the last written word line.

FIG. 24 illustrates the bias levels applied to word lines in the coarse search.

DETAILED DESCRIPTION Memory System

FIG. 1 illustrates schematically the main hardware components of a memory system suitable for implementing the following. The memory system 90 typically operates with a host 80 through a host interface. The memory system may be in the form of a removable memory such as a memory card, or may be in the form of an embedded memory system. The memory system 90 includes a memory 102 whose operations are controlled by a controller 100. The memory 102 comprises one or more array of non-volatile memory cells distributed over one or more integrated circuit chip. The controller 100 may include interface circuits 110, a processor 120, ROM (read-only-memory) 122, RAM (random access memory) 130, programmable nonvolatile memory 124, and additional components. The controller is typically formed as an ASIC (application specific integrated circuit) and the components included in such an ASIC generally depend on the particular application.

With respect to the memory section 102, semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.

The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.

In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.

By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.

Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.

Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.

It will be recognized that the following is not limited to the two dimensional and three dimensional exemplary structures described but cover all relevant memory structures within the spirit and scope as described herein

Physical Memory Structure

FIG. 2 illustrates schematically a non-volatile memory cell. The memory cell 10 can be implemented by a field-effect transistor having a charge storage unit 20, such as a floating gate or a charge trapping (dielectric) layer. The memory cell 10 also includes a source 14, a drain 16, and a control gate 30.

There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may employ different types of memory cells, each type having one or more charge storage element.

Typical non-volatile memory cells include EEPROM and flash EEPROM. Also, examples of memory devices utilizing dielectric storage elements.

In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding conduction current with respect to a fixed reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.

Alternatively, instead of detecting the conduction current among a partitioned current window, it is possible to set the threshold voltage for a given memory state under test at the control gate and detect if the conduction current is lower or higher than a threshold current (cell-read reference current). In one implementation the detection of the conduction current relative to a threshold current is accomplished by examining the rate the conduction current is discharging through the capacitance of the bit line.

FIG. 3 illustrates the relation between the source-drain current I_(D) and the control gate voltage V_(CG) for four different charges Q1−Q4 that the floating gate may be selectively storing at any one time. With fixed drain voltage bias, the four solid I_(D) versus V_(CG) curves represent four of seven possible charge levels that can be programmed on a floating gate of a memory cell, respectively corresponding to four possible memory states. As an example, the threshold voltage window of a population of cells may range from 0.5V to 3.5V. Seven possible programmed memory states “0”, “1”, “2”, “3”, “4”, “5”, “6”, and an erased state (not shown) may be demarcated by partitioning the threshold window into regions in intervals of 0.5V each. For example, if a reference current, IREF of 2 μA is used as shown, then the cell programmed with Q1 may be considered to be in a memory state “1” since its curve intersects with I_(REF) in the region of the threshold window demarcated by VCG=0.5V and 1.0V. Similarly, Q4 is in a memory state “5”.

As can be seen from the description above, the more states a memory cell is made to store, the more finely divided is its threshold window. For example, a memory device may have memory cells having a threshold window that ranges from −1.5V to 5V. This provides a maximum width of 6.5V. If the memory cell is to store 16 states, each state may occupy from 200 mV to 300 mV in the threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.

NAND Structure

FIG. 4 illustrates schematically a string of memory cells organized into a NAND string. A NAND string 50 comprises a series of memory transistors M1, M2, . . . Mn (e.g., 4, 8, 16 or higher) daisy-chained by their sources and drains. A pair of select transistors S1, S2 controls the memory transistor chain's connection to the external world via the NAND string's source terminal 54 and drain terminal 56 respectively. In a memory array, when the source select transistor S1 is turned on, the source terminal is coupled to a source line (see FIG. 5). Similarly, when the drain select transistor S2 is turned on, the drain terminal of the NAND string is coupled to a bit line of the memory array. Each memory transistor 10 in the chain acts as a memory cell. It has a charge storage element 20 to store a given amount of charge so as to represent an intended memory state. A control gate 30 of each memory transistor allows control over read and write operations. As will be seen in FIG. 5, the control gates 30 of corresponding memory transistors of a row of NAND string are all connected to the same word line. Similarly, a control gate 32 of each of the select transistors S1, S2 provides control access to the NAND string via its source terminal 54 and drain terminal 56 respectively. Likewise, the control gates 32 of corresponding select transistors of a row of NAND string are all connected to the same select line.

When an addressed memory transistor 10 within a NAND string is read or is verified during programming, its control gate 30 is supplied with an appropriate voltage. At the same time, the rest of the non-addressed memory transistors in the NAND string 50 are fully turned on by application of sufficient voltage on their control gates. In this way, a conductive path is effectively created from the source of the individual memory transistor to the source terminal 54 of the NAND string and likewise for the drain of the individual memory transistor to the drain terminal 56 of the cell.

FIG. 4B illustrates an example of a NAND array 210 of memory cells, constituted from NAND strings 50 such as that shown in FIG. 4. Along each column of NAND strings, a bit line such as bit line 36 is coupled to the drain terminal 56 of each NAND string. Along each bank of NAND strings, a source line such as source line 34 is coupled to the source terminals 54 of each NAND string. Also the control gates along a row of memory cells in a bank of NAND strings are connected to a word line such as word line 42. The control gates along a row of select transistors in a bank of NAND strings are connected to a select line such as select line 44. An entire row of memory cells in a bank of NAND strings can be addressed by appropriate voltages on the word lines and select lines of the bank of NAND strings.

FIG. 6 illustrates a page of memory cells, organized in the NAND configuration, being sensed or programmed in parallel. FIG. 6 essentially shows a bank of NAND strings 50 in the memory array 210 of FIG. 5, where the detail of each NAND string is shown explicitly as in FIG. 4. A physical page, such as the page 60, is a group of memory cells enabled to be sensed or programmed in parallel. This is accomplished by a corresponding page of sense amplifiers 212. The sensed results are latched in a corresponding set of latches 214. Each sense amplifier can be coupled to a NAND string via a bit line. The page is enabled by the control gates of the cells of the page connected in common to a word line 42 and each cell accessible by a sense amplifier accessible via a bit line 36. As an example, when respectively sensing or programming the page of cells 60, a sensing voltage or a programming voltage is respectively applied to the common word line WL3 together with appropriate voltages on the bit lines.

Physical Organization of the Memory

One difference between flash memory and other of types of memory is that a cell must be programmed from the erased state. That is the floating gate must first be emptied of charge. Programming then adds a desired amount of charge back to the floating gate. It does not support removing a portion of the charge from the floating gate to go from a more programmed state to a lesser one. This means that updated data cannot overwrite existing data and must be written to a previous unwritten location.

Furthermore erasing is to empty all the charges from the floating gate and generally takes appreciable time. For that reason, it will be cumbersome and very slow to erase cell by cell or even page by page. In practice, the array of memory cells is divided into a large number of blocks of memory cells. As is common for flash EEPROM systems, the block is the unit of erase. That is, each block contains the minimum number of memory cells that are erased together. While aggregating a large number of cells in a block to be erased in parallel will improve erase performance, a large size block also entails dealing with a larger number of update and obsolete data.

Each block is typically divided into a number of physical pages. A logical page is a unit of programming or reading that contains a number of bits equal to the number of cells in a physical page. In a memory that stores one bit per cell, one physical page stores one logical page of data. In memories that store two bits per cell, a physical page stores two logical pages. The number of logical pages stored in a physical page thus reflects the number of bits stored per cell. In one embodiment, the individual pages may be divided into segments and the segments may contain the fewest number of cells that are written at one time as a basic programming operation. One or more logical pages of data are typically stored in one row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data.

All-Bit, Full-Sequence MLC Programming

FIG. 7A-7C illustrate an example of programming a population of 4-state memory cells. FIG. 7A illustrates the population of memory cells programmable into four distinct distributions of threshold voltages respectively representing memory states “0”, “1”, “2” and “3”. FIG. 7B illustrates the initial distribution of “erased” threshold voltages for an erased memory. FIG. 6C illustrates an example of the memory after many of the memory cells have been programmed. Essentially, a cell initially has an “erased” threshold voltage and programming will move it to a higher value into one of the three zones demarcated by verify levels vV₁, vV₂ and vV₃. In this way, each memory cell can be programmed to one of the three programmed states “1”, “2” and “3” or remain un-programmed in the “erased” state. As the memory gets more programming, the initial distribution of the “erased” state as shown in FIG. 7B will become narrower and the erased state is represented by the “0” state.

A 2-bit code having a lower bit and an upper bit can be used to represent each of the four memory states. For example, the “0”, “1”, “2” and “3” states are respectively represented by “11”, “01”, “00” and ‘10”. The 2-bit data may be read from the memory by sensing in “full-sequence” mode where the two bits are sensed together by sensing relative to the read demarcation threshold values rV₁, rV₂ and rV₃ in three sub-passes respectively.

3-D NAND Structures

An alternative arrangement to a conventional two-dimensional (2-D) NAND array is a three-dimensional (3-D) array. In contrast to 2-D NAND arrays, which are formed along a planar surface of a semiconductor wafer, 3-D arrays extend up from the wafer surface and generally include stacks, or columns, of memory cells extending upwards. Various 3-D arrangements are possible. In one arrangement a NAND string is formed vertically with one end (e.g. source) at the wafer surface and the other end (e.g. drain) on top. In another arrangement a NAND string is formed in a U-shape so that both ends of the NAND string are accessible on top, thus facilitating connections between such strings.

FIG. 8 shows a first example of a NAND string 701 that extends in a vertical direction, i.e. extending in the z-direction, perpendicular to the x-y plane of the substrate. Memory cells are formed where a vertical bit line (local bit line) 703 passes through a word line (e.g. WL0, WL1, etc.). A charge trapping layer between the local bit line and the word line stores charge, which affects the threshold voltage of the transistor formed by the word line (gate) coupled to the vertical bit line (channel) that it encircles. Such memory cells may be formed by foiming stacks of word lines and then etching memory holes where memory cells are to be formed. Memory holes are then lined with a charge trapping layer and filled with a suitable local bit line/channel material (with suitable dielectric layers for isolation).

As with planar NAND strings, select gates 705, 707, are located at either end of the string to allow the NAND string to be selectively connected to, or isolated from, external elements 709, 711. Such external elements are generally conductive lines such as common source lines or bit lines that serve large numbers of NAND strings. Vertical NAND strings may be operated in a similar manner to planar NAND strings and both SLC and MLC operation is possible. While FIG. 8 shows an example of a NAND string that has 32 cells (0-31) connected in series, the number of cells in a NAND string may be any suitable number. Not all cells are shown for clarity. It will be understood that additional cells are formed where word lines 3-29 (not shown) intersect the local vertical bit line.

A 3D NAND array can, loosely speaking, be formed tilting up the respective structures 50 and 210 of FIGS. 5 and 6 to be perpendicular to the x-y plane. In this example, each y-z plane corresponds to the page structure of FIG. 6, with m such plane at differing x locations. The (global) bit lines, BL1-m, each run across the top to an associated sense amp SA1-m. The word lines, WL1-n, and source and select lines SSL1-n and DSL1-n, then run in x direction, with the NAND string connected at bottom to a common source line CSL.

FIGS. 9-12 look at a particular monolithic three dimensional (3D) memory array of the NAND type (more specifically of the “BiCS” type), where one or more memory device levels are formed above a single substrate, in more detail. FIG. 9 is an oblique projection of part of such a structure, showing a portion corresponding to two of the page structures in FIG. 5, where, depending on the embodiment, each of these could correspond to a separate block or be different “fingers” of the same block. Here, instead to the NAND strings lying in a common y-z plane, they are squashed together in the y direction, so that the NAND strings are somewhat staggered in the x direction. On the top, the NAND strings are connected along global bit lines (BL) spanning multiple such sub-divisions of the array that run in the x direction. Here, global common source lines (SL) also run across multiple such structures in the x direction and are connect to the sources at the bottoms of the NAND string, which are connected by a local interconnect (LI) that serves as the local common source line of the individual finger. Depending on the embodiment, the global source lines can span the whole, or just a portion, of the array structure. Rather than use the local interconnect (LI), variations can include the NAND string being formed in a U type structure, where part of the string itself runs back up.

To the right of FIG. 9 is a representation of the elements of one of the vertical NAND strings from the structure to the left. Multiple memory cells are connected through a drain select gate SGD to the associated bit line BL at the top and connected through the associated source select gate SDS to the associated local source line LI to a global source line SL. It is often useful to have a select gate with a greater length than that of memory cells, where this can alternately be achieved by having several select gates in series, making for more uniform processing of layers. Additionally, the select gates are programmable to have their threshold levels adjusted. This exemplary embodiment also includes several dummy cells at the ends that are not used to store user data, as their proximity to the select gates makes them more prone to disturbs.

FIG. 10 shows a top view of the structure for two blocks in the exemplary embodiment. Two blocks (BLK0 above, BLK1 below) are shown, each having four fingers that run left to right. The word lines and select gate lines of each level also run left to right, with the word lines of the different fingers of the same block being commonly connected at a “terrace” and then on to receive their various voltage level through the word line select gates at WLTr. The word lines of a given layer in a block can also be commonly connected on the far side from the terrace. The selected gate lines can be individual for each level, rather common, allowing the fingers to be individually selected. The bit lines are shown running up and down the page and connect on to the sense amp circuits, where, depending on the embodiment, each sense amp can correspond to a single bit line or be multiplexed to several bit lines.

FIG. 11 shows a side view of one block, again with four fingers. In this exemplary embodiment, the select gates SGD and SGS at either end of the NAND strings are formed of four layers, with the word lines WL in-between, all formed over a CPWELL. A given finger is selected by setting its select gates to a level VSG and the word lines are biased according to the operation, such as a read voltage (VCGRV) for the selected word lines and the read-pass voltage (VREAD) for the non-selected word lines. The non-selected fingers can then be cut off by setting their select gates accordingly.

FIG. 12 illustrates some detail of an individual cell. A dielectric core runs in the vertical direction and is surrounded by a channel silicon layer, that is in turn surrounded a tunnel dielectric (TNL) and then the charge trapping dielectric layer (CTL). The gate of the cell is here formed of tungsten with which is surrounded by a metal barrier and is separated from the charge trapping layer by blocking (BLK) oxide and a high K layer.

Reducing Read Disturb in Partially Written Blocks

Performing an operation, such as a read, write or erase, on one location of a memory like those described above can affect the quality of data stored on another location of the memory, an effect called a “disturb”. For example, due to capacitive coupling between memory cells on adjacent word line (or “Yupin-effect”), a voltage applied along one word line can affect the state of the memory cells on adjacent word lines. In the case of NAND memory, whether of the 2D or 3D variety, when reading a selected word line, non-selected word lines along shared NAND strings must also be biased. Referring back to FIG. 6, to read memory cells along WL3 requires that the cells along the other word lines be conducting. This is done by applying a voltage VREAD to all non-selected word lines (WL0-2 and WL4-n in this example) that is high enough so that non-selected memory cells on these word lines conduct regardless of the data state they hold. For example, for the states illustrated in FIGS. 7A-C, VREAD needs to be higher than the threshold voltages of the highest state's distribution. The cells on these non-selected word lines will then conduct and the cells along selected word lines can then be read by applying a sensing voltage VCG_R (such as one of the sensing voltages, such as rV₁, rV₂, or rV₃ in FIG. 7A) along the selected WL3. The application of this relatively high VREAD level can be a cause of read disturb, particularly for erased memory cells.

Word lines are typically written sequentially starting from one end, such as with the source end with WL0 in FIG. 6, and working through to WLn on the drain side. This section looks at techniques to reduce read disturbs on partially written blocks (“PBRD”), such as would happen when the memory system performs binary scan to find the last written page and for host reads to the block. This sort of binary scan is sometimes known as Last Written Page Detection or Find Last Good Page (LWPD/FLGP). Reads to partial written blocks are governed by host usage. There are multiple occasions when system may need to check for last written page, such as during write abort recovery, power interruption, and so on. Some memory system use a flag that is stored with a graceful power shutdown. In such events the boundary in known and LWPD/FLGP can be avoided, but not on all open blocks (especially the block in which the flag needs to be stored). In the case of ungraceful shutdown, the system needs to scan and identify if there was a power interruption during open block program or during idle time.

One way of doing last written page detection is with a binary scan to search for first page which reads ALL FF (fully erased). The last written page is the one before the first page which reads ALLFF. The scanning algorithm and pattern detection is typically done off-chip with a discrete controller chip. This incurs overhead associated with commands and data transfers. In multi-die systems, the scan times scale with the number of NAND chips per controller and can run into timeout constraints.

During these binary scans, the high bias VREAD is applied on drain side relative to the word lines being read. (In this example, the word lines are written in sequence from the source to the drain side.) The more the number of times last written page detection is done, the more drain side word lines are subjected to the high bias VREAD. As exposure to the high bias VREAD increases, drain side word lines can accumulate significant amount of disturb. Hence, when the system comes back and writes the previously unwritten drain side word lines, high bit error rate (BER) can be seen on drain side word lines. This situation is similar to read disturb on partial written blocks that happens on erased, un-written word lines when reading written word lines several times. In the case of LWPD, the boundary page (last written word line) is not yet known, so that it is not possible to apply methods which have a priori knowledge of the partial block boundary page.

The combination of NAND and the sequential writing of data pages onto word lines leads to a much higher level of read disturb on partially written blocks relative to fully written blocks. The reasons for the high bit error rate (BER) for the partially written block case can be explained by considering the partially written block case relative to the fully written block. In the case of a partially written block, only a few word lines may be written in a block, with the higher word lines in the write sequence still being erased. Some of the written word lines are read multiple times, with the higher word lines, that are erased, seeing the high VREAD bias that causes accumulated disturb. When the system comes back and writes the remaining word lines of the block higher word lines see read disturb followed by Yupin-effect word line to word line capacitive coupling during programming. For the fully written case, were all of the word lines have been written, some of the written word lines may also be read multiple times; but for the higher word lines that are already written, they see the high VREAD after Yupin-effect in the write process.

The higher BER is seen for the partially written block case since the higher, unwritten word lines see the read disturb first, while still erased, followed by the Yupin-effect during the subsequent write. (More detail on, and techniques related to, error arising from partial block reads is discussed in U.S. patent application Ser. No. 14/526,870 filed on Oct. 29, 2014.) For the fully written block, the latter word lines see the program related Yupin-effect first, followed by the read disturb. Since the amount of disturb is independent of initial erase depth, the erased state shifts up more when Yupin-effect is seen after disturb, i.e. for partial block case, resulting in a high BER. As a consequence, when doing binary search for last written page detection or reading data from the written pages, the system can expect a high BER on erased/un-written word lines after the whole block is written.

As noted above, one way to find the last written page of a block is to perform a binary search of the block's word lines, a technique that can lead to a large number of reads, and corresponding bit error rates, on partially written blocks. To reduce the bit error rate, the following describes the use of a reduced VREAD level for some of the non-selected word lines, a technique that can be extended to data reads. When doing a last written page search, the reduced VREAD technique can also be used to intelligently skip word lines when searching through a block from one end to the other. Further, to improve performance during a last written page search, whether in a binary search or when searching from the end, reduced settling times can be used.

To determine the last written of a sequentially written set of word line, it is not necessarily provide an accurate read of the data along the word line, but just to determine whether it has been written or is still in an erased state. The described techniques can be implemented as an on-chip, auto-scan feature for last written page detection. When performing the sensing operation, a lower VREAD (or VREAD_PARTIAL) is applied to drain side word lines (that is, the word lines written latter in the write sequence order). The sensing operation with the reduced VREAD_PARTIAL can also be used to determine how many word lines to skip in the process based on how may bits are read as a “1”.

Considering these in turn and looking at the lowered VREAD level, in a standard sensing operation for a NAND type memory the non-selected word lines need to biased to a level that allows them to conduct for any programmed data state; however, for an unwritten word line, the erased memory cells will turn on at a lower voltage, the using of which will result less disturb on the unprogrammed cells. Consequently, when searching for the last written word line, when performing a read some or all of the word lines later in the write order than the word can have applied the lower VREAD_PARTIAL; using the example where word lines are written in order from the source end of the NAND strings, VREAD_PARTIAL can be applied to all word lines on the drain side of the selected word line. This can be illustrated with respect to FIG. 13.

The left-most column in FIG. 13 shows the word line numbers, where these are numbered in the sequential order in which they are written, starting in this example with WL0 on the source side and working toward WL64 on the drain/bit line end. The last written word line is here taken to be WL_i. In the read of the left “Bias”, WL0 selected and all the other word line receive the VREAD_PARTIAL level. As the word lines from WL1 to WL_i are written, some cells along these word lines may not conduct for VREAD_PARTIAL so that this modified sensing operation may not yield an accurate data read, yielding a false “1”, but it will allow a determination of whether WL0 has been written. Similarly, for a word line WL_n as shown in the middle “Bias” column, the word lines on the source side (WL0 to WL_n−1) need to not contribute and are set at the full VREAD, while the (potentially unwritten) WL_n+1 to WL64 are set at VREAD_PARTIAL. The process would be done similarly, with similar results, for all word lines up to and including the last written word line WL_i, the only difference being that the read of WL_i would be an accurate read. For WL_i+1 in the right “Bias” column, the written word lines WL0 to WL_i will all receive VREAD and be conducting; VREAD_PARTIAL is only applied to unwritten word lines WL_i+2 to WL64, so they will also be conducting; and the sensing voltage VCG_R on WLj+1 will accurate indicate that it has not been written.

The use of the lower VREAD_PARTIAL can help to reduce the disturb accumulated on drain side erased word lines, thereby reducing bit error rates. This is shown in the plot of FIG. 14, that is based on device data and where the horizontal axis is the number of read cycles and the vertical axis is an indication of bit error rates along a word line. The behavior of a fully written block is shown at 1401 and for a partially written block that uses the full VREAD for all word line at 1403. In this example, VREAD is on the order of several volts. The effect of reducing VREAD_PARTIAL incrementally by about 7%, 10%, and 20% relative to VREAD is respectively shown at 1405, 1407, and 1409. As shown on the plot, reducing VREAD_PARTIAL by around 20% relative to VREAD will significantly reduce disturb on partially written blocks to a level similar to disturb on wholly written blocks.

In the embodiment illustrated with respect to FIG. 13, all of the word lines on the drain of the selected word line are set to VREAD_PARTIAL. In other cases, it may be more practical to set only some of these word lines at the lower level; for example, if word line decoding uses a zone structure, where word lines are grouped into contiguous sets, it may make sense to apply VREAD_PARTIAL to only the word lines of entire zones that fall on the drain side of the currently selected word line. As to the level used for VREAD_PARTIAL relative to the standard VREAD, this can be a fixed offset or can depend on the device's age, number of program/erase cycles the block has seen, number of word lines, or other factors.

The use of the reduced VREAD_PARTIAL when searching for the last written page can be used for a binary search as well as other algorithms. For instance, the search can be made by progressing from the source end to drain end, skipping word lines along the way where, as alluded to above, the result of reading a written word line with the lowered VREAD_PARTIAL can be used as part of an intelligent algorithm to decide how many word lines to skip.

The Last Written Page Detection (LWPD) can be sped up by skipping some number of word lines, but still having some or all of the drain side word lines at a lower bias VREAD_PARTIAL. Due to the NAND structure, the number of “1”s in the pattern will be a logical “AND” of all the word lines at VREAD_PARTIAL. As the number of word lines at VREAD_PARTIAL decreases, the number of “1's” decreases; and as level of VREAD_PARTIAL decreases, the number of “1”s decreases. So measuring the number of “1”s at a given voltage can provide an estimate of the distance to the true boundary. Consequently, an exemplary scan algorithm can base the number of skipped word lines on the number of “1” bits read after the scan: if “1” bits are less than a criterion, then the presumption is that it is far from the boundary and the algorithm can do a big step for skipped number of word lines; otherwise, a smaller step of fewer word lines is used. Depending upon the VREAD_PARTIAL bias, the criteria for skipping WLs can be set.

This is illustrated in the plot of FIG. 15, where horizontal axis is the number of word lines between the selected word line and the last written word line, and the vertical axis is the expected number of “1” bits. This example is for a 2 bit per cell embodiment, where the states are labelled Er, A, B, C in order of increasing thresholds. The voltage VRC is used to distinguish between the B and C states and is shown at 1501; the voltage VRB is used to distinguish between A and B states and is shown at 1503; and the VRA voltage is used to distinguish between the Er and A states and is shown at 1505.

Say, for example, the algorithm starts with VREAD_PARTIAL close to VRB (i.e., all cells with B-state/C-state on drain side WLs will cut-off the NAND string and hence, will make threshold voltages on selected word lines appear high, i.e. as a 0-bit) due to an increase in NAND string resistances. If the algorithm uses can a criterion of, say, 16 bits, then it can step˜8 word lines without having to worry about over-stepping past the last written word line. Then, switching to a VREAD_PARTIAL to close to VRA, it can step˜4 word lines until the time criteria of 16 bits is reached. Finally, it can switch to 1 word line at a time until getting an ALL FF result. FIG. 16 illustrates such an algorithm.

The flow of FIG. 16 starts at 1601 and at 1603 WL0 is read using a VREAD_PARTIAL level close to VRB. At 1605 it is determined whether the read at 1603 meets the criterion of ALL FF values being greater than, in this example, 16 bits. If yes, the selected word line value is incremented at 1607 by 8 and the process loops back to 1605. If the criterion is not met, the word line value is only incremented by 4 at 1609 and the flow goes to 1611. The selected word line is then read at 1613, where the VREAD_PARTIAL level is dropped down to near the VRA level. The read result is then compared to the criterion at 1613: if passes, n incremented by 4 at 1609 before looping back to 1611; if “No”, the count is incremented by 1 at 1615 before being read at 1617 checked against the criterion at 1619. If 1619 gives a “Yes”, the process loops back to 1615; if “No”, the last written word line is WL_n−1 (1621), at which point the flow ends (1623). This algorithm can speeds up the LWPD search, while only subjecting the drain side word lines to VREAD_PARTIAL, reducing disturb issues on partially written blocks. A number of variations on this algorithm can be used, including backing up in case of over-shoot or a hybridized binary search.

For any of the LWPD algorithms, whether using a reduced VREAD_PARTIAL or not, the process can be accelerated by performing the ALL-FF detection with smaller bit line settling times. In a sensing operation, before the sensing voltage is applied to the selected word line, it is usual to settle some voltage level on the bit lines in order accurately read the page. As a LWPD need not read the data as accurately, this is one reason why the settling time can be shorted. Another reason is that the bit lines should also settle more quickly in a partially written block since all of the unwritten bit lines will have the same data (namely, all in an erased state), reducing the effect of differing states on different bit lines has on how quickly settling can occur. This effect is illustrated in FIG. 17. In FIG. 17, the number of incorrect bits (FBC) is plotted against bit line settling times.

These various aspects can all help to accelerate the LPWD process so that a process that previously would need to involve the controller can now be done by the memory chip itself. In such a last page to be written search, it is not known up front which pages are not written, but many these aspects described above can also be applied to reading partially written blocks in a data read operation when there is prior knowledge of which pages are unwritten.

When performing a read to extract a page of data along a word line of NAND memory, the non-selected word lines are biased so that they will conduct independently of the stored data. For the standard VREAD, this needs to be a level above the threshold of the highest states. If the memory system knows that a block is only partially written, and knows which of the word lines are unwritten, a lower VREAD_PARTIAL can be used on some or all of these unwritten word lines, reducing their disturb level while still allowing them to conduct. This lower VREAD_PARTIAL can be used on all of the unwritten word lines, even where these are not written sequentially, or a subset, such as when word lines are organized as zones and only fully unwritten zones use the lowered value.

FIG. 18 is an example of a simplified box diagram to illustrate the situation. A host 1821 sends a read command the memory system 1801, where the memory system could a memory card, embedded memory system, solid state drive (SSD) and so on. The memory system 1801 is here taken to be formed of a controller 1811 and a number of memory chips, only one of which is shown at 1803; and on the memory chip 1803, only an array 1805 divided into multiple blocks is explicitly represented. A host typically bases a read command on a logical address that the controller the controller then converts into a corresponding physical address for where the data is stored on the memory circuit. The logical address is received at the controller 1811, where the logic circuitry/firmware 1813 use conversion information, typically stored in RAM 1815, to obtain the physical address used when passing the read command on to the memory circuit. Based on the physical address, the logic circuitry/firmware 1813 can also determine whether the corresponding block is only partially written, where this could also be done based on a list stored in RAM 1815. Alternately, the memory chip itself could make the determination that the read command is for a partially written block.

In one implementation, when sending the read command from the controller 1811 to the memory 1803, the logic circuitry/firmware 1813 can send an additional prefix command with, say, 1 byte address to the NAND memory 1803 indicating where the written/unwritten word line boundary is. Once the boundary in known by the NAND, it can setup the voltages on the word lines beyond the written area accordingly. Similarly, for multi-plane operation, a prefix can be issued separately for each plane, as the open block may be written up to a different page (n−1) on different planes. The word line/page information can be used to approximate the boundary if a group of word lines are part of the same driver circuit. In this case the exact boundary need not be used, but set at the edge of the zone.

In the preceding, the read was initiated by the host, but this technique can also be applied to reads originating on the memory circuit itself, such as arise in data relocation or data scrub operations. The read can be for user data or for system data reads, where the latter more typically have partially written blocks (and often more sensitive data) due to its nature.

One set of examples of where sensing operations are performed on partially written, or “open”, blocks is for verify operations, both those done between programming pulses and for post-write read verifications, such as for Enhanced Post Write Read (EPWR) operations. The memory system performs reads on the open blocks frequently for operations like “rolling” EPWR, such as where EPWR is performed on a word line WLn−1 when the adjacent word line WLn has just completed a program stage. This kind of open block reads can cause read disturb on the drain side word lines since they are in Erased state, which frequently leads to uncorrectable ECC (UECC) events or higher BER on those word lines. If the memory circuit has a mode to read open blocks with a lower bias on the un-programmed word lines, then it can help to resolve this issue.

With knowledge of first un-programmed word line, the memory circuit can use this information to apply a lower VREAD bias on all the word lines including and above the un-programmed word line. As with the above discussion, the memory circuit can either keep track of this information during the write process or the controller can pass the address of the first un-programmed word line to the memory through a series of address and commands preceding the actual command sequence to read. The memory can then apply this lower VREAD bias on the word lines when the first erased word line is within a certain range of the word line that is selected for sensing.

For example, the controller can issue a command and address sequence to read the NAND memory having a first portion to indicate that the following address cycle will specify the address of the first erased word line. This command is one that can be latched only on the selected chip and have, say, 1 Byte to specify the address of the un-programmed word line and that can be reset at the end of a read operation. If the first un-programmed word line falls within a certain range of the word line that is being read, a low bias (VREAD_PARTIAL above or, more succinctly, VPVD in the following) can be applied to all the un-programmed word lines. An example of this range is specified in Table 1. This example shows the word lines spit into 14 word line zone (control gate, or CG, zones), the corresponding word line ranges, the word line at which the lower VREAD (VPVD) starts.

TABLE 1 Selected CG Zone Selected WL VPVD start WL 1 <=WL16 <=WL24 2 WL17-WL24 <=WL33 3 WL25-WL32 <=WL41 4 WL33-WL40 <=WL49 5 WL41-WL48 <=WL57 6 WL49-WL56 <=WL65 7 WL57-WL64 <=WL73 8 WL65-WL72 <=WL81 9 WL73-WL80 <=WL89 10 WL81-WL88 <=WL97 11 WL89-WL96  <=WL105 12  WL97-WL104  <=WL113 13 WL105-WL112  <=WL121 14 WL113-WL127  <=WL127

FIG. 19 is an exemplary flow for using a lower VREAD bias on un-programmed word lines, such as can be done as part of a post write read verification process. At 1901 a byte (Addr1) specifying the first un-written word line (WLvpvd) is provided from the controller. (Alternately, if the memory tracks or determines the first unwritten word line, the determination can be made internally.) It is then determined (1903) whether the first un-written word line is zero (block written) or if it is below the selected word line (WLsel) and, if so (1905), the usual word line biasing is used. If not, and the WLvpvd value specifies an end zone (zones 1 and 14 in the example of Table 1), the reduced VPVD bias is used on all the word lines starting from the specified value. If for a non-end zone, the proximity of the specified word line to the selected word line is determined at 1909 and if far enough away the VPVD value is used starting at WLvpvd (1913) and if not far enough away the usual read bias is used (1911).

FIG. 20 is a flow of an example of a simplified embodiment, where the memory applies a lower VREAD bias on the un-programmed word lines only if the first un-programmed word line is within an 8 word line range of the selected word line. The flow again begins with receiving the location of the first un-written word line at 2001. Relative to 1903, the decision at 2003 now also considers whether the first un-programmed word line is within an 8 word line range of the selected word line (WLvpvd>WLsel+8). The “Yes” path then leads to use of the usual word line biases (2005), while the “No” path applies (2007) the reduced VPVD on all word lines starting from that specified in 2001.

Alternate Boundary Word Line Search

This section looks an alternate method for finding the last written word line of a partially written block, where the word lines of a block are split up into several zones in order to find in which zone the last programmed WL resides. The memory can then perform a fine search of the identified zone to find the exact location of the last programmed word line.

For example, the coarse step involves dividing the word lines, on which the memory cells of the NAND chains of the block are connected, into, say, 4 zones with each zone having 31-33 word lines. (Different number of zones in both coarse and fine steps can be used, as this is a design choice, and the number of word lines per zone will depend on the number word lines in a block, where it is generally being more efficient to use more or less equal sized zones at each step.) Assuming that word lines are written sequentially from the lower (source) end of the NAND strings, the memory can then sense the NAND chains by applying a high VREAD bias on the lowermost zone and a low VREAD bias(or VPVD) on rest of the zones. (If the word lines are instead written starting at the top, or drain, end, the process would instead go from highest to lowest.) Here VREAD can be the standard bias level for non-selected word lines in a sensing operation, which needs to be high enough for a cell to conduct for any of the data states written into it. The VPVD bias level is lower than VREAD, to reduce disturb, but needs to allow an erased cell to conduct. If all the NAND chains are conducting, this would indicate that the last programmed word line lies in the lower zone or zones with all of the word lines set at VREAD. (More generally, rather than require all NAND chains conduct, an option is to allow a few non-conducting chains, such as by adding a parameter for this.) If the NAND strings are not conducting, then the method can continue the search by extending the VREAD bias to the next zone, continuing this process until it finds the zone that causes some of the NAND chains to become non-conducting when VPVD bias is applied to that zone. This way the system narrows the search down to a zone of word lines that has the boundary WL.

The identified coarse zone can then be sub-divided into, for example, four smaller zones of 8 word lines each and use the same approach as for the coarse zones to narrow down further into a group of 8 word lines that have the last programmed word lines. While executing this fine step, all the word lines below the selected zone are biased at VREAD and all the word lines above the selected zone are biased at VPVD. Note that unlike in the previous section, where the determination was made with respect to a specific word line set at a sensing voltage, here the determination is made on a zone basis, with only the regular non-selected word line VREAD and the lower VPVD. This can simplify the decoding, both in that a sensing voltage is not needed and in that VREAD and VPVD levels are applied at the zone level.

Once narrowed down to an 8 word line zone, the process can either continue to follow this approach to narrow down to the last written WL by dividing the bigger zone into smaller zones (such as 2 word lines each) or, alternatively, by conducting a binary search on the 8 word line zone.

Considering the method further, the exemplary algorithm to search for the boundary word line in an open block can be divided into a coarse search and a fine search. Taking an example of where blocks have 128 word lines, in the NAND chains can be divided in to four zones, such as shown in Table 2.

TABLE 2 WL# Zone(N)  0-32 1 33-64 2 65-96 3  97-127 4 Starting a N=1, the block is sensed with VREAD on word lines in zone 1 and below and the low bias on zones N+1 and above. The number of non-conducting NAND chains is then counted, such as by counting the number of 0's in the corresponding data latches, and compared to a criterion. The criterion can be fixed or it can be a memory parameter that can be set by the user. If the number of non-conducting NAND chains is less than the criterion, this corresponds to the last programmed word line being in Zone-N. In this case, the process jumps to the Fine Search. If the number of non-conducting NAND chains is higher than the criterion, the last programmed WL is in zones N+1 or above, in which case, the process sets N=N+1 and repeats the sensing and counting.

FIG. 21 is a flow chart for a coarse search phase and FIG. 22 is schematic representation of the zone level biasing for an exemplary embodiment. In FIG. 22 the left-most columns lists the adjacent sets of word lines that are in the corresponding one of zones 1-4 as shown in the next column. As shown in the left-most, the example of FIGS. 21 and 22 illustrates the use of differing zone sizes that can optimized to the device. For this example, the first and last zones have a different size (33 and 31 word lines, rather than 32) to accommodate various boosting modes that could be used during programming. The next four columns show the zone biasing for the four iterations of boundary determining the sense operation, where VREAD is applied to the lower zones and the lower VPVD to the upper zones. For example, if the NAND strings conduct with biasing for N=1, but did not conduct with the biasing of N=0, this would correspond to the last written word line being in zone 2. Note that the N=3 biasing is optional since if the block is not fully written, but still did not conduct at the N=2 biasing, then the last written word line would lie in zone 4.

Backing up to the flow of FIG. 21, the flow begins setting N=0 at 2101, with a read using the corresponding bias conditions as shown in FIG. 22 at 2103. The number of non-conducting word lines is counted at 2105 and at 2107 it is checked to see if the count meets the criterion: If so, the last written word line is in the corresponding zone, zone N+1; if not, the value of N is incremented at 2109 and the flow loops back to 2103 for the next zone, if there is one. When the criteria is met, the last written word line's zone is then determined. In this example using different sized zones at the end, the end zones are considered at 2113 and medial zones at 2115.

FIGS. 23 and 24 illustrate the fine search for an exemplary embodiment. As shown in FIG. 24, the identified zone is subdivided into four sub-zones and biased similarly to FIG. 22, where the word lines below WLk will be at Vread and the word lines above WLk+31 will be at VPVD. As with the coarse search, three sensings are needed to determining which subdivision has the last written word line, where the fourth sensing can be used as a check, if desired. In the fine search flow of FIG. 23, the flow begins at 2301 by starting with the first sub-division of the zone identified in the coarse search. At 2303 it is biased as illustrated in FIG. 24 and sensed, with the number of non-conducting NAND strings is counted at 2305. The count is checked at 2307 and if the count is not below the criterion, the flow loops back to 2303 after K being incremented at 2309. As the subdivisions at this point are of 8 word lines, K is incremented by 8. (In the exemplary embodiment, Zone 0 of the coarse search was taken to have 33 word lines and this is reflected in different incrementation for K=0.) As with the coarse flow, if the sense was at the next to last subdivision, the NO result from 2307 can continue to 2311 using the last of the subdivisions.

If the criterion is met at 2307, the subdivision is established (2311) and it can then be subdivided again and the process repeated (2313) in order determine the last written word line at 2315.

The techniques of this section can be implemented in a fully digital manner and do not rely upon a judgment based upon statics of the data patterns written along the NAND strings. As such, it is applicable to all data patterns, including pure 0 and pure 1 patterns, even when the number of allowed non-conducting NAND chains is set at zero. As the exemplary embodiments do not rely upon analog circuitry to distinguish between highly conducting and less conducting NAND chains, is very accurate and avoids the need to do a backwards scan once it has narrowed the search down to a particular zone, sub-zone or WL. As there is no requirement of additional high-voltage switches on the memory circuit, the techniques of this section can be implemented in an area efficient manner.

CONCLUSION

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the above to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to explain the principles involved and its practical application, to thereby enable others to best utilize the various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto. 

1. A method comprising: dividing word lines of a block of a non-volatile memory into a plurality of zones, the zones comprising pluralities of contiguous word lines; determining to which of the zones the last written word line belongs, by biasing word lines of a selected zone to a first read voltage biasing the word lines of one or more zones between the selected zone and a first end of the block to the first read voltage and biasing word lines of one or more zones between the selected zone and a second end of the block to a second read voltage, wherein the first read voltage is sufficient to allow memory cells of the block to conduct independently of a data state programmed thereto and the second read voltage is less than the first read voltage; and in response to determining that a number of non-conducting strings of the block satisfies a first criterion, determining that the last written word line of the block belongs to the selected zone;
 2. The method of claim 1, wherein the first read voltage is a voltage level applied to non-selected word lines of a selected memory block during a standard read operation.
 3. The method of claim 1, wherein the second read voltage is a voltage level that allows the memory cells to conduct for less than all of the data states that may be programmed thereto.
 4. The method of claim 3, wherein the second read voltage is a voltage level that allows the memory cells to conduct only if in an erased state.
 5. The method of claim 1, wherein the first criterion comprises the number of non-conducting strings of the block being zero.
 6. The method of claim 1, wherein the first criterion is a settable parameter.
 7. The method of claim 1, further comprising: sub-dividing the word lines of the determined zone into a plurality of sub-zones, each of the sub-zones having contiguous word lines; and determining to which of the sub-zones the last written word line belongs, by performing one or more sensing operations on a corresponding one or more of the sub-zones.
 8. The method of claim 7, wherein performing ef a sensing operation on a selected sub-zone comprises biasing word lines of the selected sub-zone to the first read voltage.
 9. The method of claim 1, wherein in determining to which of the zones the last written word line belongs, zone read operations are performed sequentially on the zones starting from the first end of the block until the zone to which the last written word line belongs is determined.
 10. The method of claim 1, wherein the non-volatile memory comprises a monolithic semiconductor memory device where the memory cells are arranged in a two-dimensional array.
 11. The method of claim 1, wherein the non-volatile memory comprises a monolithic three-dimensional semiconductor memory device having the memory cells arranged in multiple physical levels above a silicon substrate and comprising a charge storage medium, wherein the strings run in a vertical direction relative to the substrate, and wherein the word lines run in a horizontal direction relative to the substrate.
 12. A system, comprising: an array of non-volatile memory cells having a plurality of blocks in which memory cells of a block are formed along a plurality of word lines, including a first word line, and in which the word lines of a the block are written sequentially from a first end to a second end of the block; and a controller for the array of non-volatile memory cells, the controller performing a write operation on the first word line of the block and performing a post-write read operation for the first word line in response to a read command indicating unwritten word lines of the block, the post-write read operation including: applying a first sensing voltage along the first word line; applying a first non-selected word line read voltage along word lines between the first word line and the first end of the block; and applying a second non-selected word line read voltage along one or more of the indicated unwritten word lines between the first word line and the second end of the block, wherein the second non-selected word line read voltage is less than the first non-selected word line read voltage.
 13. The system of claim 12, wherein in the post-write read operation, the second non-selected word line read voltage is applied to all of the word lines between the first word line and the second end of the block, the block comprising a partially written block.
 14. The method system of claim 12, wherein the word lines of the block are divided into a plurality of zones, each zone formed of a distinct plurality of adjacent word lines, and wherein in the post-write read operation, for word lines other than the first word line, the first non-selected word line read voltage is applied along word lines of the zone to which the first word line belongs, and the second non-selected word line read voltage is applied to all of the word lines between the zone to which the first word line belongs and the second end of the block.
 15. (canceled)
 16. The system of claim 12, wherein the controller maintains a list of partially written blocks and determines whether the first word line belongs to a partially written block by comparing a physical address of the first word line to the list.
 17. The system of claim 12, wherein the read command is sent from the controller in response to determining that the first word line belongs to a partially written block.
 18. The system of claim 17, wherein the read command includes a prefix indicating a modified read operation and the unwritten word lines of the partially written block.
 19. (canceled)
 20. (canceled)
 21. The system of claim 12, wherein the array of non-volatile memory cells are formed on a non-volatile memory circuit that is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.
 22. An apparatus comprising: a controller for a semiconductor memory device, the controller configured to: locate a last written word line in a partially written block of the semiconductor memory device by biasing word lines of different zones of the block to different read voltages and determining whether a number of non-conducting strings of the block satisfy a criterion; apply a first non-selected word line read voltage to one or more word lines between a first end of the partially written block and the last written word line in a read operation for the partially written block; and apply a second non-selected word line read voltage to one or more word lines between the last written word line and a second end of the partially written block in the read operation, the second non-selected word line read voltage being less than the first non-selected word line read voltage.
 23. The apparatus of claim 22, wherein the controller is configured to locate the last written word line by: dividing word lines of the partially written block into the different zones, each zone comprising contiguous word lines; biasing word lines of a selected zone and one or more zones between the selected zone and the first end of the partially written block to a third read voltage; and biasing word lines of one or more zones between the selected zone and the second end of the partially written block to a fourth read voltage, wherein the fourth read voltage is less than the third read voltage; and in response to determining that the number of non-conducting strings of the partially written block satisfies the criterion, determining that the last written word line of the block belongs to the selected zone.
 24. The apparatus of claim 22, wherein the controller is configured to send a read command for the read operation to the semiconductor memory device, the controller identifying the last written word line in the read command. 